1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device which can be used both as a static random access memory (hereinafter referred to as an SRAM) and a read only memory (hereinafter referred to as a ROM).
2. Description of the Background Art
FIG. 1 is a block diagram showing a structure of a conventional general SRAM. Referring to the figure, a plurality of word lines WL1, WL2, WL3, WL4 . . . are provided in a memory cell array 1. A plurality of bit lines BL1, BL1, BL2, BL2 . . . are arranged intersecting these word lines in the memory cell array 1.
The adjacent bit lines constitute bit line pairs. For example, bit lines BL1 and BL1 form a bit line pair, and bit lines BL2 and BL2 form a bit line pair. A memory cell 2 (shown by a hatched potion in FIG. 1) is arranged at each of the intersections between the word lines and the bit line pairs. A supply line 3 and a ground line 4 are connected to the memory cell array 1. A supply voltage Vcc (hereinafter this voltage is regarded as H level) applied to the supply line 3 and a ground voltage 0 V (hereinafter, this voltage is regarded as L level) applied to the ground line 4 are applied to each memory cell 2. A row decoder 5, a column decoder 6 and an input/output circuit 8 are provided related to the memory cell array 1. The row decoder 5 decodes a row address signal applied through an address input line 7 to select one of the plurality of word lines, and applies a voltage of H level to the selected word lines. The input/output circuit 8 comprises a plurality of switching circuits provided for respective bit line pairs, and one or a plurality of sense amplifiers posed between a data input/output line 9 and the switching circuits. The column decoder 6 decodes a column address signal applied through the address input line 7 to select one of the plurality of switching circuits in the input/output circuit 8 to render conductive the selected switching circuit. Therefore, one of the plurality of memory cells 2 is selected by the row decoder 5 and the column decoder 6.
FIG. 2 is a schematic diagram showing the structure of the memory cell 2 shown in FIG. 1. Referring to the figure, the memory cell 2 comprises N channel MOS transistors 21 and 22 forming a flipflop, high resistance load elements 23 and 24, and N channel MOS transistors 25 and 26 forming a transfer gate. Each of the high resistance load elements 23 and 24 has one end connected to the supply line 3. A transistor 21 is interposed between the other end of the high resistance load element 23 and the ground line 4. A transistor 22 is interposed between the other end of the high resistance load element 24 and ground line 4. The gate of the transistor 21 is connected to the other end of the high resistance load element 24. The gate of the transistor 22 is connected to the other end of the high resistance load element 23. A Transistor 25 is interposed between a bit line BLn (n is an arbitrary positive integer) and the high resistance load element 23. A transistor 26 is interposed between the bit line BLn and the other end of the high resistance load element 24. The gates of transistors 25 and 26 are connected to corresponding word lines WLn.
The writing and reading operations of the conventional SRAM shown in FIGS. 1 and 2 will be described in the following.
Writing Operation
First, a word line WLn is selected by the row decoder 5, and a voltage of H level is applied to the word line WLn. Consequently, the transistors 25 and 26 are turned on. A switch circuit corresponding to the bit line pair BLn, BLn out of the plurality of switching circuits in the input/output circuit 8 is rendered conductive by the column decoder 6. Consequently, write data are applied to the bit line pair BLn, BLn through the data input/output line 9. Assuming that a voltage of H level is applied to the bit line BLn and a voltage of L level is applied to the bit line e,ovs/BL/ n as the write data at this time, the nodes e and c of FIG. 2 attain to the H level, and the transistor 22 is turned on. Consequently, the potential at the node d attains to the L level, and the transistor 21 is kept off. Therefore, the potential at the node c is pulled up through the high resistance load element 23 to maintain the H level. Accordingly, the potential of the node c is set to the H Level, and the potential of the node d is set to the L level. This state is regarded as a state in which the memory cell 2 stores the logic "1". Meanwhile, if a voltage of L level is applied to the bit line BLn and a voltage of H level is applied to the bit line BLn as the write data, an operation completely opposite to the above operation is carried out. Namely, the transistor 21 is turned on and the transistor 22 is kept off. Consequently, the potential of the node c is set to the L level, while the potential of the node d is set to the H level. The state is regarded as a state in which the logic "0" is stored.
Reading Operation
First, a word line WLn is selected by the row decoder 5. Consequently, the transistors 25 and 26 are turned on, and potentials set at the nodes c and d are read to the bit lines BLn and BLn. Namely, if the logic "1" is stored in the memory cell 2, the bit line BLn attains to the H level, and the bit line BLn attains to the L level. If the logic "0" is stored, the bit line BLn attains to the L level, and the bit line BLn attains to the H level. The reading operation is carried out for all the memory cells 2 belonging to the word line WLn selected by the row decoder 5. Thereafter, a switching circuit corresponding to the bit line pair BLn and BLn is selected to be rendered conductive, out of the plurality of switches in the input/output circuit 8, by the column decoder 6. Consequently, read data of one memory cell only is applied to a sense amplifier in the input/output circuit 8 through the selected switching circuit to be applied to the data input/output line 9, out of the memory cells 2 of one row selected by the row decoder 5. Consequently, the information stored in the selected one memory cell is read from the data input/output line 9.
In the conventional SRAM shown in FIGS. 1 and 2, each memory cell 2 is capable of static storing of information, provided that the supply voltage Vcc is supplied to the supply line 3. Namely, unlike the dynamic RAM in which memory cells must be refreshed in a prescribed period, the information stored in the memory cells 2 are maintained. However, in the conventional SRAM described above, the information stored in the memory cells 2 are erased when the supply of the supply voltage to the supply line 3 is stopped. Namely, the conventional SRAM has no function of fixedly storing information, that is, the function of a ROM.
However, as various and many systems have been developed recently, semiconductor memory devices having various functions have come to be in great demand. Semiconductor memory devices having functions of both SRAM and ROM have been strongly desired.